- Formal Verification
- Symbolic Computer Algebra
- Arithmetic Circuits
- Complexity of Verification Techniques
- High-Level Synthesis
- This website provides formal verification solutions based on Symbolic Computer Algebra (SCA) for complex arithmetic circuits, such as multipliers.
- GenMul is a multiplier generator which outputs multiplier circuits in Verilog. The input size of a multiplier and each multiplier stage can be configured with GenMul.