Alireza Mahzoon

Alireza Mahzoon

Ph.D. Student & Researcher

Book Contributions

  1. Alireza Mahzoon, Daniel Große, and Rolf Drechsler. GenMul: Generating architecturally complex multipliers to challenge formal verification tools. In Recent Findings in Boolean Techniques, pages 177-191. Springer, 2021.

Journals

  1. Alireza Mahzoon, Daniel Große, and Rolf Drechsler. RevSCA-2.0: SCA-based Formal Verification of Nontrivial Multipliers Using Reverse Engineering and Local Vanishing Removal. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2021.

  2. Alireza Mahzoon and Bijan Alizadeh. Systematic Design Space Exploration of Floating-point Expressions on FPGA. IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS II), 64 (3), pages 274-278, 2016.

  3. Alireza Mahzoon and Bijan Alizadeh. OptiFEX: A Framework for Exploring Area-efficient Floating Point Expressions on FPGAs with Optimized Exponent/Mantissa Widths. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ISVLSI), 25 (1), pages 198-209, 2016.

Conferences

  1. Alireza Mahzoon and Rolf Drechsler. Polynomial Formal Verification of Prefix Adders. In Asian Test Symposium (ATS), 2021.

  2. Mehran Goli, Alireza Mahzoon, and Rolf Drechsler. Automated Debugging-aware Visualization Technique for SystemC HLS Designs. In Euromicro Conference on Digital System Design (DSD), 2021.

  3. Alireza Mahzoon and Rolf Drechsler. Late Breaking Results: Polynomial Formal Verification of Fast Adders. In Design Automation Conference (DAC), 2021.

  4. Christoph Scholl, Alexander Konrad, Alireza Mahzoon, Daniel Große, and Rolf Drechsler. Verifying Dividers Using Symbolic Computer Algebra and Don’t Care Optimization. In Design, Automation and Test in Europe Conference (DATE), 2021.

  5. Mehran Goli, Alireza Mahzoon, and Rolf Drechsler. ASCHyRO: Automatic Fault Localization of SystemC HLS Designs Using a Hybrid Accurate Rank Ordering Technique. In International Conference on Computer Design (ICCD), pages 179-186, 2020.

  6. Alireza Mahzoon, Daniel Große, Christoph Scholl, and Rolf Drechsler. Towards Formal Verification of Optimized and Industrial Multipliers. In Design, Automation and Test in Europe (DATE), pages 544-549, 2020.

  7. Alireza Mahzoon, Daniel Große, and Rolf Drechsler. RevSCA: Using Reverse Engineering to Bring Light into Backward Rewriting for Big and Dirty Multipliers. In Design Automation Conference (DAC), pages 185:1-185:6, 2019.

  8. Alireza Mahzoon, Daniel Große, and Rolf Drechsler. PolyCleaner: Clean your Polynomials before Backward Rewriting to Verify Million-gate Multipliers. In International Conference on Computer Aided Design (ICCAD), pages 129:1-129:8, 2018. (Best Paper Award)

  9. Alireza Mahzoon, Daniel Große, and Rolf Drechsler. Combining Symbolic Computer Algebra and Boolean Satisfiability for Automatic Debugging and Fixing of Complex Multipliers. In IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pages 243-248, 2015.

  10. Alireza Mahzoon and Bijan Alizadeh. Multi-objective Optimization of Floating Point Arithmetic Expressions Using Iterative Factorization. In IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pages 351-356, 2018.

Workshops

  1. Alireza Mahzoon and Rolf Drechsler. Polynomial Formal Verification of Prefix Adders. In International Workshop on Logic & Synthesis (IWLS), 2021. (Best Student Paper Candidate)

  2. Alireza Mahzoon and Rolf Drechsler. Polynomial Formal Verification of Area-efficient and Fast Adders. In 2021 Reed-Muller Workshop (RM2021), 2021.

  3. Alireza Mahzoon, Daniel Große, and Rolf Drechsler. GenMul: Generating Architecturally Complex Multipliers to Challenge Formal Verification Tools. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2021.

  4. Alireza Mahzoon, Daniel Große, and Rolf Drechsler. GenMul: Generating Architecturally Complex Multipliers to Challenge Formal Verification Tools. In International Workshop on Logic & Synthesis (IWLS), 2019.

  5. Alireza Mahzoon and Bijan Alizadeh .HOFEX: High Level Optimization of Floating Point Expressions for Implementation on FPGAs. In International Workshop on Logic & Synthesis (IWLS), 2015.