Alireza Mahzoon is a Ph.D. candidate in the institute of Computer Science at the University of Bremen. He received the B.Sc. degree in Electrical engineering from the K. N. Toosi University of Technology, Tehran, Iran, in 2013, and M.Sc. degree in Digital Systems from the School of Electrical and Computer Engineering (ECE) at the University of Tehran (UT), Tehran, Iran, in 2016. He is currently a member of the Group of Computer Architecture (AGRA) working with Prof. Rolf Drechsler and Prof. Daniel Große.

News

August 6, 2021: Our paper Polynomial Formal Verification of Prefix Adders has been accepted at the Asian Test Symposium (ATS 2021)

July 22, 2021: Our work on Polynomial Formal Verification of Prefix Adders will be presented at the 30th International Workshop on Logic & Synthesis (IWLS 2021)

July 15, 2021: Our paper Polynomial Formal Verification of Prefix Adders has been nominated for the Best Student Paper award at the 30th International Workshop on Logic & Synthesis (IWLS 2021)

June 23, 2021: Our paper Polynomial Formal Verification of Prefix Adders has been accepted at the 30th International Workshop on Logic & Synthesis (IWLS 2021)

June 15, 2021: our work on Automated Debugging-Aware Visualization Technique for SystemC HLS Designs has been accepted at the Euromicro Conference on Digital System Design (DSD 2021)

May 24, 2021: our work on Late Breaking Results: Polynomial Formal Verification of Fast Adders has been accepted at the 58th Design Automation Conference (DAC 2021)

May 4, 2021: Our paper RevSCA-2.0: SCA-based Formal Verification of Non-trivial Multipliers using Reverse Engineering and Local Vanishing Removal has been accepted for publication in the journal IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)